Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask).
The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. One of the primary enabling factors of this growth has been the ability of optical lithography to steadily decrease the smallest feature size that can be formed as part of the integrated circuit pattern. The steady decline in feature size and cost and the corresponding increase in the density of features printed per circuit are commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask or reticle (mask and reticle are used interchangeably herein), then projecting an image from the mask onto a resist-covered semiconductor wafer in order to create a pattern that matches the design intent of defining functional elements, such as transistor gates, contacts etc., on the wafer. The more times a master pattern is successfully replicated on a wafer within the design specifications, the lower the cost per finished device or “chip” will be. Until recently, the mask pattern has been an almost exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern, due to an imaging reduction ratio of the exposure tool. The mask is typically formed by depositing and patterning a light absorbing material on quartz or another transparent substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the wafers. The light is transmitted through clear areas of the mask, but is attenuated by a desired amount, typically between 90 and 100%, in the areas covered by the absorbing layer. The light that passes through some regions of the mask may also be phase shifted by a desired phase angle, typically an integer multiple of 180 degrees. After being collected by the projection optics of the exposure tool, the resulting aerial image pattern is then focused onto the wafers. A light-sensitive material (photoresist or resist) deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well-known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the mask pattern onto the wafer. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose contrast and sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture (NA) of the exposure tool times the minimum feature size Wf divided by the wavelength λ, i.e., k1=NA·Wf/λ. There is limited practical flexibility in choosing the exposure wavelength, while the numerical aperture of exposure tools is approaching physical limits. Consequently, the continuous reduction in device feature sizes requires more and more aggressive reduction of the k1 factor in lithographic processes, i.e. imaging at or below the classical resolution limits of an optical imaging system.
New methods to enable low-k1 lithography have used master patterns on the mask that are no longer exact copies of the final wafer level pattern. The mask pattern is often adjusted in terms of the size and placement of pattern features as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask pattern (“serifs,” “hammerheads,” and other patterns) known as Optical Proximity Correction, or OPC; and the addition of other geometries that are not intended to be replicated on the wafer at all. The sole purpose of these non-printing “assist features,” also known as Sub-Resolution Assisting Features (SRAFs) or scattering bars, is to enhance the printability of the “main features.” The SRAFs are typically small bars placed close to the main features so that the printability of the main features is more robust against focus and/or dose change. All of these methods are often referred to collectively as Resolution Enhancement Technology (RET). With decreasing k1, the magnitude of proximity effects increases dramatically. In current high-end designs, more and more device layers require RET, and almost every feature edge requires some amount of adjustment to ensure that the printed pattern will reasonably resemble the design intent. The implementation and verification of such extensive RET application is only made possible by detailed full-chip computational lithography process modeling, and the process is generally referred to as model-based RET. (See “Full-Chip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design,” C. Spence, Proc. SPIE, Vol. 5751, pp. 1-14 (2005) and “Exploring New High Speed, Mask Aware RET Verification Flows,” P. Martin et al., Proc. SPIE 5853, pp. 114-123, (2005)).
The cost of manufacturing advanced mask sets is steadily increasing. Currently, the cost has already exceeded one million dollars per mask set for an advanced device. In addition, the turn-around time is always a critical concern. As a result, lithography-driven RET design, which assists in reducing both the cost and turn-around time, has become an integral part of the semiconductor manufacturing process.
FIG. 1 is a flowchart of a prior art method for applying resolution enhancement techniques to a design layout. In step 110, a design layout that describes the shapes and sizes of patterns that correspond to functional elements of a semiconductor device, such as diffusion layers, metal traces, contacts, and gates of field-effect transistors, is obtained. These patterns represent the “design intent” of physical shapes and sizes that need to be reproduced on a wafer by the lithography process in order to achieve certain electrical functionality and specifications of the final device. The design layout is also referred to as the “pre-RET” layout or target pattern
As described above, numerous modifications to this design layout are required to create the patterns on the mask or reticle used to print the desired structures. In step 112, a variety of RET methods are applied to the design layout in order to approximate the design intent in the actually printed patterns. The resulting “post-RET” mask layout often differs significantly from the “pre-RET” design layout. Both the Pre- and Post-RET layouts may be provided to the lithography simulation system in a polygon-based hierarchical data file, for example, but not limited to, the GDS or the OASIS format.
In step 114, as one example, resist contours on the wafer are simulated using the post-RET layout and a model of the lithography process. This model includes an optical model component that describes the transformation from the post-RET layout to an aerial image (AI) and a resist model component that describes the transformation from the AI to the final resist image (RI). In step 116, the simulated resist contours are extracted from the RI and compared to the target design layout, and in step 118 it is determined whether the simulated resist contours are acceptable (i.e., within a predefined error tolerance). If they are not acceptable, then the method returns to step 112 where another iteration of RET methods are applied to the pre-RET layout. If the simulated resist contours are acceptable, then the post-RET layout is output and used to manufacture an actual mask (Step 120).
A central part of lithography simulation is the optical model component of the model of the lithography process, which simulates the projection and image forming process in the exposure tool. The optical model needs to incorporate critical parameters of the illumination and projection system, such as but not limited to, numerical aperture and partial coherence settings, illumination wavelength, illuminator source shape, and possibly imperfections of the system such as aberrations or flare. The projection system and various optical effects, e.g., high-NA diffraction, scalar or vector, polarization, and thin-film multiple reflection, may be modeled utilizing transmission cross coefficients (TCCs). The TCCs may be decomposed into convolution kernels, using an eigen-series expansion. For computation speed, the series is usually truncated based on the ranking of eigen-values, resulting in a finite set of kernels. The more kernels that are kept, the less error is introduced by the truncation. The lithography simulation system described in U.S. Pat. No. 7,003,758, which is hereby incorporated herein in its entirety, allows for optical simulations using a very large number of convolution kernels without negative impact on computation time and therefore enables highly accurate optical modeling.
As the lithography process entered below the 65 nm node, leading-edge chip designs have minimum feature sizes smaller than the wavelength of light used in advanced exposure tools. Sub-resolution assist features (SRAFs) become indispensable even if OPC techniques provide good results. Typically, OPC will modify the design layout so that a resist image (RI) contour is close enough to the design target at nominal condition. However, the Process Window (PW) is rather small without any extra features. SRAFs are needed to enhance the printability of the main features across a wider range of defocus and delta dose scenarios in order to maintain adequate process margins in the lithography process.
For the layout itself, the relative position of main feature patterns are also playing an important role in the PW size. For example, for 1-dimensional patterns, designs must avoid forbidden pitches, which are a period of repetitive patterns that result in very low printability. For certain forbidden pitches, no SRAF or OPC can help yield desirable PW. For 1-dimensional patterns (such as a line and space pattern), it is relatively easy to determine a set of rules to avoid a forbidden pitch in the layout design. However, a typical chip design consists of many patterns with complicated 2-dimensional geometric shapes and no simple rules can provide a design which avoids bad placement of layout (for example, due to a forbidden pitch) and also makes efficient use of the space.
Accordingly, there is a strong need for a method and/or process for improving the mask formation process so as to further improve the resulting imaging performance, beyond the corrections available utilizing known OPC techniques, which can accommodate complicated and different 2-dimensional target patterns.